1. Field of the Invention
The present invention relates to selectable programmable timing delay circuits to provide a synchronous clock signal to a number of remote modules in a synchronous system.
2. Description of the Related Art
In a synchronous system a clock signal is provided to all parts of the system which is synchronized, or delivered in phase, with a minimum margin of error. The propagation of the clock signal to various parts of the system will cause the phase of the clock due to the propagation delays in the communication link among the various parts of the system to skew. When the parts of the system are located on modules which are remote from the clock which generates the clock signal, the propagation delay can be significant, leading to an unacceptable skew in the clock signal at various modules and can cause system malfunctions. Thus, the propagation delay in the communication link which transmits the clock signal must be equalized in order to provide the synchronous clock necessary for running the system.
U.S. Pat. 4,805,195 entitled "Selectable Timing Delay Circuit" provides a selectable or programmable timing delay circuit which allows the clock signal to be synchronized at remote modules in a given system, without powering down the system and without requiring manual soldering or other cumbersome techniques during the set up of the machine.
One use of such a selectable tuning delay circuit is to have a selectable tuning delay circuit manufactured as an integrated circuit and placed on a board with other integrated chips to form a selectable delay timing system. Such a system is shown in FIG. 1 wherein the clock is received at input 11 of board 10. The board is comprised of chips 12, 13 and 14 wherein chip 13 contains the integrated circuit for the tuning delay circuit. The output, point 15, provides a delayed clock. The delay of the clock from input point 11 to output point 15 is specified as a specific delay (Ts) plus or minus a tolerance delay (ts). Since board 10 is to be manufactured in quantity, the tuning delay circuit 12 must be designed to account for the process variations of the various chips used on the board. In FIG. 1, the process variations of chip 12, chip 13 and chip 14 must be taken into account to ensure that the tuning delay circuit chip 13 has sufficient range (Tr) and resolution (tr) to meet the requirements of the specified delay (Ts) and the delay tolerance (ts).
Each chip that is manufactured has a specified nominal delay (N) and an absolute process variation (V) for the delay to take into account the varying speed of chips, of the same type, manufactured by the manufacturer. The problem is exemplified in FIG. 2. The delay associated with a board would have a minimum nominal delay, obtained by having the tuning delay circuit set at its minimum delay, and a nominal maximum delay, obtained by setting the tuning delay circuit to its maximum delay. The range between the minimum nominal delay and the maximum nominal delay would be the tuning range of the timing delay circuit on the board. When process variations are taken into account, FIG. 2 illustrates that fast chips will result in a minimum and maximum delay which occurs earlier than if nominal values were used and that slow chips will result in minimum and maximum delays which occur later in time than had nominal chips been used.
In that when the board is manufactured, it is unknown what the characteristics of the chips used on the board will be, the problem arises to design a tuning delay circuit capable of tuning the system to obtain the desired specified delay within the specified tolerances.